A generic communication link comprises a transmitter, communication channel, and receiver. A Serializer-Deserializer (SerDes) receiver is an example of a device that processes analog signals transmitted through a channel, and the SerDes receiver typically includes components to compensate for impairments introduced by the channel. Such impairments typically include added noise and inter-symbol interference characterized by the transfer function of the communication channel. A SerDes receiver includes equalization, for which the datapath typically includes a combination of a Continuous-Time Linear Equalizer (CTLE), a Feed Forward Equalizer (FFE), a Decision Feedback Equalizer (DFE), and various adaptation circuits employed to adapt the various equalizer and filter parameters.
As the serial data stream in a SerDes system is transmitted over a single data link without clock forwarding, the receiver must extract the timing information from the data stream to retime the data. A clock and data recovery (CDR) circuit is usually employed that both extracts timing for a local sampling clock from the sampled data and samples/quantizes the input signal. The accuracy of this operation performed in the CDR circuit is limited by the jitter affecting the received data edges, sometimes referred to as the jitter tolerance (JTOL). A pattern generator of a standardized jitter tolerance source for system compliancy verification generates various bit patterns to test performance of a receiver. For example, a pattern generator of a standardized jitter tolerance source for system compliancy verification generates a so-called compliant jitter tolerance pattern (CJTPAT), composed of the data words representing the worst case condition for jitter tolerance measurement of the receiver, as a means to test JTOL. Other test patterns are known, such as a SAS training pattern, a CRTPAT pattern, and a PN23 pseudo random pattern, for testing jitter tolerance. This testing enables a SerDes implementation to exhibit a relatively good jitter tolerance for similar patterns in actual serial data traffic.
Existing least mean square (LMS) and group delay based adaptation algorithms work well for sufficiently randomized data. When data exhibiting single or dual tones persist in the receive data, these known adaptation algorithms fail to achieve a relatively optimal state during operation. A pattern detector assists in avoiding equalizer adaptation to a known data pattern that might lead to sub-optimal adaptation results. However, the known methods of pattern detection to protect the equalizer adaptation process against harmful patterns only allows for detection of single tones in the receive data, and do not provide for detection of the dual tone which is characteristic to, for example, a CJTPAT test signal.
In addition, the known methods do not address low activity detection, which might lead to possible drifting of the CDR circuit sampling point from the middle location of the data eye. Drifting of the CDR circuit sampling point from the middle location of the data eye, in turn, might make LMS or group delay algorithms misbehave immediately after the end of the low activity region in the receive data. The known methods also do not include a delay in enabling adaptation after the “bad” pattern. Such a delay may be needed for the CDR to regain lock to the center of the eye. Known methods also do not address an exact implementation of equalization adaptation freeze (a point in time when the equalizer's adaptation process is frozen to prevent gross errors in filter/equalizer values during adaptation updates), which might present a significant challenge for aligning of the freeze with adaptation algorithm word size and latency.